The present invention disclosed herein relates to semiconductor memory devices, and more particularly, to nonvolatile memory devices and related methods.
Semiconductor memories are widely used as fundamental microelectronic components in applications with digital logic circuits such as computers and in systems using microprocessors ranging from satellites to customer electronics. Improved performance may be provided by improving processing techniques to allow that scaling-down for high integration density and high frequency operation.
Semiconductor memory devices may be classified as volatile and nonvolatile memory devices. In volatile semiconductor memory devices, logical information is stored by setting a logical condition of a bistable flipflop loop (as in a static random access memory) or by capacitive charging (as in a dynamic random access memory). A volatile semiconductor memory may store and read data when power is available, but may lose data when power is cut off.
A nonvolatile semiconductor memory devices may be able to maintain data stored therein even when power is cut off or suspended. A storage condition in a nonvolatile memory device may be designed to be immutable or re-programmable in accordance with fabrication techniques. A nonvolatile semiconductor memory device may be effectively used to store program files and/or micro-codes widely over applications such as computers, aerospace electronic engineering, communications, and customer electronics. As a special case, nonvolatile RAMs (nvRAMs) may be employable in systems requiring frequent and fast combinations between storage modes of volatile and nonvolatile conditions and being in need of re-programmable nonvolatile memories. In addition, nonvolatile RAMs are being studied for applications with specific memory architectures that include additional logic circuits to improve functions for application-oriented works.
Among nonvolatile semiconductor memories, MROM, PROM, and EPROM may be inconvenient to renew storage contents by general users because they are designed not to easily erase and write data therein. An EEPROM may be electrically erased and programmable with data, so it may be used for systemic programming operations that continuously require updating of data, or for auxiliary storage units.
Flash memory devices are nonvolatile memories that are electrically erasable and programmable read-only memories (EEPROMs) in which plural memory blocks are erased or written with data by one operation of programming. An EEPROM is operable such that all memory cells of one memory block are erasable or programmable at the same time. A flash memory may operate more rapidly and effectively in reading and writing data when systems employing such flash memory devices read and write data from and into other memory areas at the same time. All kinds of flash memories or EEPROMs may be configured such that insulation films enclosing charge storage elements used for storing data may be worn out after a specific number of operations.
A flash memory may store information even without power. A flash memory may be able to retain information/data stored therein without power consumption even after interruption of a power supply to the chip. In addition, flash memories offer resistance to physical shocks and fast access times for reading. Flash memories may thus be widely used as storage units in electronic apparatuses powered by batteries.
In a generic flash memory device, bit information is stored by injecting charges into a conductive floating gate, which is isolated through an insulation film, by the Fowler-Nordheim (F-N) tunneling mechanism. However, such a conductive floating gate may have a physical limit in integration, causing capacitive couplings between memory cells or between memory cells and selection transistors (i.e., string and ground selection transistors). For the purpose of reducing capacitive couplings between conductive floating gates of cell and selection transistors, charge-trap flash memory devices may be used. A charge-trap flash memory device may use an insulation (or dielectric) film, which is made of Si3N4, Al2O3, HfAlO, or HfSiO, as a charge storage layer.
However, there may still be physical problems in a charge-trap flash memory device. A typical problem arising from the charge-trap flash memory device may be ‘erase stress’, ‘erasing stress’, or ‘erasure stress’ (hereinafter called ‘erasure stress’) that is caused while repeatedly erasing a specific memory cell without programming. In an erasing operation, the ground voltage is applied to a word line of memory cells and an erasing voltage is applied to a bulk (e.g., pocket P-well) of the memory cells, while string and ground selection transistors float. At a memory cell under this bias condition, an electric field is formed toward a control gate from the pocket P-well, resulting in hole injection to a charge storage layer of the memory cell from the pocket P-well. Then, trapped electrons are consumed by electron-hole pairs (EHPs) with the injected holes in the charge storage layer (i.e., charge trap layer). If the memory cell is repeatedly erased, more holes are injected into the charge trap layer. That is, in a charge-trap cell transistor used as a memory cell, an injection amount of holes is raised in proportion to the times of erasing cycles. An excessive increase of hole injection amount would cause inadvertent EHPs with electrons held at trap layers of adjacent memory cells. This effect means there would be variation of threshold voltages in adjacent charge-trap flash transistors. Therefore, it may be necessary for the charge-trap flash memory device to be confined in erasing cycle times, not to be continuously left on the erasing operation.